Two boards can share a ground and exchange apparently sensible signals while still operating outside their specified limits. A high level that one device produces may not be high enough for the other; a signal in the opposite direction may exceed an input rating. A level shifter solves a defined interface problem, not every incompatibility between two connectors.
This guide covers general logic connections in low-voltage DC projects. Numerical examples illustrate common arrangements, not universal thresholds or speed guarantees. The specific device and module datasheets take precedence, including their operating conditions, timing and power-sequencing requirements.
1. Four limits to compare
VOH is the guaranteed high-level output voltage under the stated conditions. VOL is the corresponding low-level output voltage. These are not necessarily equal to the supply rails: output loading, supply voltage and temperature affect the guarantees.
VIH specifies the minimum input voltage guaranteed to be recognised as high. VIL specifies the maximum input voltage guaranteed to be recognised as low. An input between those limits is generally not a valid guaranteed logic state. The device’s actual switching threshold is not a substitute for these guaranteed limits.
Compare the driver’s minimum VOH with the receiver’s minimum VIH, and the driver’s maximum VOL with the receiver’s maximum VIL. Leave noise margin rather than accepting a barely equal result. Also check the receiver’s permitted input range, input current and absolute maximum ratings; correct logical interpretation does not by itself establish electrical safety.
Find these limits in the electrical-characteristics table and read its footnotes. Check recommended operating conditions separately from absolute maximum ratings. Absolute maximum values are stress limits, not an invitation to operate continuously at their edge.
2. A 3.3V output driving a 5V input
Some 5 V CMOS inputs specify a high-level requirement of approximately 0.7 times their supply voltage. At 5 V, that illustration gives 3.5 V, above a nominal 3.3 V output. Even if a bench connection appears to work, the combination may have no guaranteed high-state margin.
Other inputs are explicitly TTL-compatible and may require about 2.0 V for a high. A suitable 3.3 V output can then be compatible, provided its guaranteed VOH under the actual load exceeds the receiver’s specified VIH. These examples describe different input designs; they do not establish a rule for every 5 V board.
Include supply tolerances and the output’s source current in the comparison. A weak output can fall below its unloaded voltage when connected to a substantial load. Check low-level compatibility too. If the documented limits leave insufficient margin, use a translator intended for those supply ranges and signal types.
3. A 5V output driving a 3.3V input
A conventional 3.3 V input may not tolerate a 5 V signal. The input can exceed its permitted range, conduct through a protection structure or suffer damage. Do not infer tolerance from a board’s operating supply or from a successful short trial.
Accept a “5 V tolerant” claim only when the exact pin’s datasheet explicitly supports the signal and conditions. Digital and analog-capable pins on the same controller can have different restrictions. Tolerance may depend on the pin function, supply being present or another operating mode.
Check both powered and unpowered limits. A tolerant input while its supply is on may still accept current into an inactive rail when that supply is off. Likewise, a series resistor does not automatically make an overvoltage input valid: any use of clamp-current limits must be expressly supported by the device documentation.
4. Back-powering and startup states
Signals can arrive before a receiving device has power. An input protection path may then pass current into its supply rail, partially powering the device through the signal connection. This can cause unexpected operation, interfere with startup or violate current limits even without immediate damage.
Review which board powers up first, which can remain connected while switched off and what each output does during reset. Include pull-ups as potential signal sources. A controller pin initially configured as an input is not necessarily held in a safe defined state.
Look for documented partial-power-down protection or power-off isolation, and check how output-enable controls must be driven. Keep outputs inactive until the relevant supplies and receivers are ready where the design requires it. Some translators impose supply-order restrictions; others explicitly permit independent sequencing. The schematic and datasheet must settle that distinction.
5. Translation methods
Resistor divider
A divider reduces a voltage in one direction; it does not raise a lower signal or actively drive the result. It can suit a documented high-impedance input and a slow, one-way signal. Include output voltage tolerance, resistor tolerance and input loading when calculating the ratio.
The divider’s resistance and the receiving input’s capacitance slow edges. Cable capacitance adds to that effect. A value that gives the expected DC voltage may fail at the intended data rate. A divider is not a general solution for bidirectional buses, precise clock timing or back-powering protection.
MOSFET and pull-ups
A suitable MOSFET-based arrangement can translate open-drain signals between pull-up rails while allowing either side to pull low. This is a common approach for I2C, where devices release the line to produce a high state rather than actively driving it high.
Its rising edges depend on the pull-up resistors and total capacitance. Check low-state voltage, sink current and supported bus speed. A generic board described as bidirectional is not automatically suitable for fast push-pull signals or every power-off condition.
Fixed or controlled direction
Buffered translators can provide a defined direction and actively driven outputs. Some use two supply rails; others use a specified input-tolerance arrangement. Choose compatible rails, adequate drive strength and propagation delay, with an appropriate inactive state.
A direction-controlled device requires that its direction signal be valid before the data path is enabled. Check each channel’s direction rather than assuming every signal in a connector travels the same way. Ordinary level translation also does not provide galvanic isolation.
Automatic direction
Automatic-direction devices remove a direction-control signal but have architecture-specific limits. Their behaviour can depend on driver strength, pull-ups, capacitance and edge acceleration. Some designs suit open-drain interfaces; others are intended for push-pull signals and cannot be treated as interchangeable.
Read the allowed load and external-resistor requirements. A device’s headline data rate can apply to a small stated capacitance, not an arbitrary cable. Ask for the complete module’s circuit before using an automatic translator on a bus it was not designed to support.
6. Match the translator to the bus
I2C needs open-drain operation and appropriate bidirectional behaviour. Data must travel both ways; clock handling may also need to support clock stretching. Confirm pull-up voltages and the total pull-up resistance on each side. Our sensor module guide covers the related module-level checks.
Conventional SPI generally has controller-to-device clock and data signals plus a return data signal. Use suitable channel directions and timing margin. Shared return lines may require high-impedance behaviour when a device is not selected; some SPI variants instead use a bidirectional data wire.
Ordinary UART has a separate direction for each transmit/receive path. Check logic-level UART, not an interface with a different electrical signalling standard. For PWM and GPIO, review pulse width, edge speed and the required state during startup. A translator that handles a slow indicator signal may not preserve a fast control pulse.
7. Method comparison
The speed contexts below are illustrative, not guaranteed ranges. Permitted speed depends on the exact circuit, supply, load and timing; use the specific datasheet. Choose from the signal’s electrical behaviour before comparing convenient connector counts.
| Method | Direction | Speed context | Suitable signals | Check carefully |
|---|---|---|---|---|
| Resistor divider | One-way reduction | Slow signals; even 9.6 kbit/s needs settling checks | Selected GPIO or low-rate receive paths | Loading, tolerance, edge delay and powered-off inputs |
| MOSFET with pull-ups | Bidirectional open-drain | For example, 100 or 400 kHz I2C only if rise-time limits are met | Compatible I2C or similar open-drain buses | Pull-up rails, sink current and low-state voltage |
| Fixed-direction buffer | Defined channel direction | kHz-to-MHz applications within the specified timing | SPI, UART, PWM or GPIO as specified | Supply range, direction and propagation delay |
| Direction-controlled translator | Selected direction | kHz-to-MHz applications; check direction-change timing | Signals with known direction changes | Direction timing and output enable |
| Automatic-direction translator | Sensed direction | kHz-to-MHz examples are device- and load-dependent | Only the bus types it explicitly supports | External resistors, drive strength and capacitance |
8. Quick checklist
- Compare guaranteed VOH with VIH and VOL with VIL.
- Include supply tolerance, temperature and output loading.
- Check each pin’s input range and absolute maximum limits.
- Require explicit evidence for any 5 V tolerance claim.
- Review unpowered inputs, reset states and supply order.
- Identify open-drain versus push-pull signalling.
- Match each channel’s direction and inactive behaviour.
- Confirm pull-ups, capacitance and timing at the intended speed.
- Check the complete module circuit, not only a translator label.
- Keep logic translation separate from isolation requirements.
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